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铁电存储器因具有非易失性、快速读写、低功耗和高耐久性操作优势,在新兴存储领域具有巨大的发展潜力。铁电随机存储器(FeRAM)依赖电荷积分的破坏性读出机制,面临高密度发展的瓶颈。高密度铁电畴壁存储器利用不同取向电畴界面的对称性缺失产生的可擦写畴壁进行信息存储,该畴壁的电导率较体材料可实现数量级的提升,可以非破坏性地读出纳米电畴信息。铁电畴壁存储器不仅继承了传统铁电随机存储器超高的读写速度和持久的擦写能力,而且还可以进行三维堆叠,极大地提升了铁电存储器的存储密度,为集成通用存储器提供了希望。本文阐述了铁电畴壁器件的研究进展;特别回顾了近年来国内外关于BiFeO3和LiNbO3等铁电畴壁存储器的研究现状;总结了目前铁电畴壁存储器在集成电路领域中所面临的技术挑战,并对其未来的发展进行了展望。
Abstract：Computers have become an indispensable part of modern society and are widely used in various fields. However, with the rapid development of data-intensive applications such as big data, the Internet of Things(IoT), artificial intelligence(AI), and automated devices, the demand for increasing computer performance continues to grow. This includes requirements of the memories for low latency, high capacity, high bandwidth, low cost, and the ability to perform human-like processing tasks. To overcome the inherent limitations of von Neumann architecture, emerging non-volatile memory(NVM) technologies have been progressively developed, including ferroelectric random-access memory(FeRAM), magnetic random-access memory(MRAM), resistive random-access memory(RRAM), and phase-change random-access memory(PCRAM). These next-generation NVM technologies aim to develop memory devices that simultaneously possess a high speed, high reliability, low power consumption, high density, and compatibility with CMOS fabrication processes. Among various emerging non-volatile memory solutions, the FeRAM has emerged as a highly promising candidate technology due to its fast write speeds, low power, and high endurance. Currently, the commercial FeRAM devices are operated based on a destructive charge integration principle, where the data are recognized by detecting different charges within bipolar ferroelectric capacitors. However, as device dimensions are scaled down, the detectable charge levels decrease proportionally to the scaled cell area, fundamentally constraining their applicability in high-capacity memory markets with the planar cell sizes above 260 nm. Meanwhile, Ferroelectric field-effect transistors(FeFETs), especially HfO_2-based devices, face challenges like small memory windows, poor retention, and limited endurance from polarization instability. The problems of switching variability and cycling reliability further hinder their adoption. Recently, researchers have increasing interest on a novel nondestructive current readout scheme in a ferroelectric domain wall memory, where the erasable domain walls under stimulating electric fields are considered as a promising platform for developing high-density ferroelectric memory devices. Though many efforts have been devoted to designing domain-wall-based memory architectures, a comprehensive review of this emerging field remains lacking. This review firstly summarizes the current research progress on the physics of ferroelectric domain walls. Ferroelectric domain walls, serving as two-dimensional interfaces separating domains with different polarization orientations, exhibit unique physical and chemical properties due to broken local symmetry. These domain walls demonstrate enhanced conductivity, unconventional magnetism, and novel optical responses compared to the bulk ferroelectric counterparts, making them promising for nanoelectronic and optoelectronic applications, including memory and sensing devices. The walls possess the atomic-scale thicknesses(a few unit cells) and can be controllably created, displaced, and erased under external stimuli(electric/mechanical fields), enabling exceptional operational flexibility in future nanodevices. Based on polarization rotation mechanisms differing in various ferroelectric materials, ferroelectric domain walls are classified into four types: Ising(gradual polarization change), Bloch(in-plane rotation), Néel(out-of-plane rotation), and mixed Ising-Néel. Ferroelectric domain walls, can be further categorized by the relative polarization angles between adjacent domains: head-to-tail/tail-to-head neutral walls, and head-to-head(H–H) or tail-to-tail(T–T) charged walls(angle α). Neutral walls exhibit zero net bound charge, while H–H/T–T charged walls accumulate free carriers(electrons/holes), leading to the enhancement of conductivity. Three mechanisms are considered to explain the enhanced domain wall conductivity: 1) defect-mediated conduction, 2) intrinsic band structure modification, and 3) local band bending induced by polarization discontinuity. The wall formation stems from the local polarization reversal, and domain switching involves nucleation, forward growth, and lateral expansion of domains. Domain wall dynamics, governed by nucleation and growth under electric fields, follow Merz's law and are influenced by stress, temperature, and defects. Understanding these dynamics is crucial for optimizing domain wall memory performance, enabling fast switching, low power consumption, and high reliability of memory devices through defect engineering. The discovery of conductive ferroelectric domain walls in insulating ferroelectrics has spurred significant interest in domain-wall-based memory devices, which utilize the creation and erasure of domain walls to produce on and off currents. After inheriting all advantages of the FeRAM and FeFETs, domain wall memories employ diverse architectures to increase the density significantly. For example, the memory cells adopting coplanar electrodes, nanostructured islands, and mesa configurations can precisely control conductive domain walls in BiFeO3 and LiNbO3. Pioneering work on BiFeO3 upon the creation and erasure of nonvolatile 71° domain walls within each cell achieved on/off ratios of >103 and multi-level storing states by modulating domain wall paths. Subsequent advances in topological domain walls(among vortex/center-type domains) increase the ratios further to 104 with endurance cycles of 108. However, the deposition of epitaxial BiFeO3 thin films at high temperatures faces challenges in integration compatible to the CMOS technologies and control of local domain switching within each cell independently. In contrast, LiNbO_3-based mesa devices using ferroelectric single crystals exhibit the excellent performance, featuring μA-scale read currents, intrinsic selector functionality for 3D stacking(enabling self-rectifying wall currents within 4×4 crossbar arrays), and 10 ns-operation speeds. Moreover, gate-tunable wall currents within three-terminal LiNbO3 transistors have exhibited logic-in-memory operations(NOT/NAND/NOR). Domain wall-based memristors have been demonstrated using sub-coercive voltage modulation for low-power operation(4 orders resistance switching) and multi-state storage. These breakthroughs highlight ferroelectric domain wall memories as a transformative technology for the development of high-density and low-power data storage devices applicable in neuromorphic computing. Summary and prospects Making use of erasable conductive channels of atomically thin domain walls, ferroelectric domain-wall memory devices achieve exceptionally high storage densities and ultrafast write/read speeds ranging from nanoseconds to picoseconds. These devices also exhibit outstanding performance of high fatigue endurance number and long-term data retention. While demonstrations of prototypical devices have validated the fundamental operation principle of domain-wall–based memories, several critical issues must be resolved before practical application. First, many novel transport phenomena observed at conductive domain walls remain inadequately understood, demanding thorough studies of domain-wall motion kinetics and the interplay between polarization, defects, and lattice coupling. Second, the domain nucleation and domain wall motion are correlated to the device reliability; therefore, precise control over domain-wall creation, propagation, and pinning is essential for ensuring fast operations and long-term data retention. Finally, in vertically stacked three-dimensional architectures, potential cross-talks between adjacent cells must be systematically evaluated especially for stable and reliable operations of multilevel memories. These challenges are crucial for advancing ferroelectric domain-wall memories toward large-scale integration and commercialization.
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基本信息:
DOI：10.14062/j.issn.0454-5648.20250376
中图分类号:TP333
引用信息:
[1]松见康平,王兴龙,胡笛等.高密度铁电畴壁存储器的研究进展[J].硅酸盐学报,2025,53(09):2489-2505.DOI:10.14062/j.issn.0454-5648.20250376.
基金信息:
国家重点研发计划(2024YFA1409500); 上海市科技创新行动计划(24CL2900900); 国家自然科学基金(62174034)